1. Field of the Invention
The present invention relates to a semiconductor design technology, and more particularly, to a compact designed integrated circuit (IC) chip by incorporating latching, level-shifting and decoding functions. The present invention can be used in a source driving device which is a display driving chip, thereby reducing a size of the driving chip.
2. Description of Related Art
In general, a display device includes a source driving device, a gate driver and a pixel array. When digital image data is stored in the pixel array of the display device, the gate driver sequentially drives a plurality of gate lines, and the source driving device stores and displays the digital image data in pixels of the pixel array coupled to the driven gate line.
FIG. 1 is a block diagram illustrating a conventional source driving device.
Referring to FIG. 1, the conventional source driving device includes a shift register 20, a sampling latch 30, a hold latch 40, a level shifter 50, a pre-decoder 60, a decoder 70, and an output buffer 80.
The shift register 20 shifts a start pulse SP input from outside, e.g., a controller, in response to a clock signal CLK. The sampling latch 30 samples digital image data R/G/B input from the controller in response to a plurality of shift signals S1 to SN output from the shift register 20. The hold latch 40 stores the sampled digital image data R/G/B during a horizontal scan time in response to a horizontal sync signal HSYNC.
The level shifter 50 shifts and converts voltage levels of the stored digital image data R/G/B in the hold latch 40 to thereby provide the voltage levels to the pre-decoder 60 since the hold latch 40 operates under low voltage condition such as 0.6 V to 3.3 V while the decoder 70 and the output buffer 80 operate under high voltage condition such as 3.8 V to 18 V. The pre-decoder 60 pre-decodes the digital image data R/G/B output from the level shifter 50 to thereby output the pre-decoded digital image data to the decoder 70.
The decoder 70 decodes the pre-decoded digital image data to thereby provide corresponding one of a plurality of gradation voltages V0 to VZ generated from a gradation voltage generator (not shown) to the output buffer 80. Herein, the decoder 70 performs a function of a digital to analog converter (DAC). The output buffer 80 buffers the gradation voltages V0 to VZ output from the decoder 70 to thereby output them to an output pad 90. The gradation voltages V0 to VZ output from the output pad 90 are provided to a pixel array of a display panel.
As described above, the conventional source driving device includes a latch, a level shifter, a pre-decoder, a decoder, and an output buffer at each channel. Herein, since the pre-decoder and the decoder following after the level shifter are composed of plural transistors for a high voltage, the size of the source driving device becomes large. In particular, lots of transistors for a high voltage are used because the pre-decoder is composed of NAND gates. For a reliability test, a test is required to apply a high voltage stress to the pre-decoder and thus a test circuit for this test is also required to use transistors for a high voltage. Furthermore, it takes lots of time to test the pre-decoder.
Hereinafter, referring to FIG. 2, the test for the pre-decoder is explained in detail.
FIG. 2 is a circuit diagram of a conventional pre-decoder with respect to one channel.
Referring to FIG. 2, the pre-decoder includes a pre-decoding unit 210 and an input unit 220. The pre-decoding unit 210 includes sixteen four-input NAND gates, each of which comprising plural transistors for a high voltage. The input unit 220 includes four inverters for inputting a logic high level or a logic low level to each input terminal of the NAND gates, thereby applying a high voltage stress to the pre-decoder. Here, each inverter also comprises a plurality of transistors for a high voltage.
As described above, the conventional source driving device includes the pre-decoder composed of the NAND gates. Each NAND gate uses four PMOS transistors for a high voltage and four NMOS transistors for a high voltage. Furthermore, for a reliability test, a test circuit is required to apply a high voltage stress to each input terminal of the pre-decoder and thus this test circuit is also required to use transistors for a high voltage. It is possible to test the pre-decoder by replacing the high voltage stress with data applied to the pre-decoder of the source driving device without additional test circuits.
In FIG. 2, to apply the high voltage stress to the NAND gates of the pre-decoder with respect to one channel, total sixteen times high voltage stress are input to the input unit 220 with an input value from ‘0000’ to ‘1111’. Accordingly, it takes lots of time to test the pre-decoder.
As described above, the conventional source driving device forms a considerably large chip size due to lots of transistors for a high voltage, and requires lots of time for the reliability test.